Axiom Design Automation is a company focused on providing the best-in-class verification platform to address the growing complexity of today’s FPGAs, ICs, SOCs and systems.
Axiom’s flagship product, MPSim is the state-of-the-art, industry proven high performance Verilog and SystemVerilog simulator integrated with the most advanced debugger, compiled testbench automation, multiple clock domain verification and comprehensive coverage analysis for quick verification closure.
MPSim: A Complete Verification Platform
MPSim incorporates SystemVerilog and OpenVera testbench automation with SVA and coverage analysis in a single kernel architecture for maximum performance.
With the complexity of today’s designs, the verification challenge has shifted. In the past the focus was at RTL and emphasis was on the simulator speed to get the fastest RTL simulation possible. But today the problem is lot more complex. In addition to RTL you now have testbenches, assertions, coverage and a complex set of debugging requirements to deal with. While a high performance simulator is required for verification, pure speed by itself is not necessarily going to increase productivity and enable you to complete your project on time.
RTL performance has to be complemented and matched by high performance engines for testbenches, assertions and coverage analysis.
These engines have to be combined with an intuitive powerful debugging environment that addresses all of these aspects simultaneously in a unified manner and is tightly integrated with the simulator in a single kernel architecture for maximum throughput and increased productivity.
From their combined experience of over fifty years of doing verification and developing simulators, Axiom team identified three key areas that are necessary to be addressed in unison to achieve fast and complete verification closure. These are Performance, Productivity and Predictability. From its inception MPSim has been designed to address these three key areas in a single kernel architecture.
MPSim is the only simulator that was designed from the beginning to address RTL, testbenches, assertion, coverage and debugging in a single kernel architecture for maximum performance productivity and predictability.