MCDV: Multiple Clock Domain Verification and Analysis

For designs with multiple, synchronous clock domains, finding errors in synchronization is virtually impossible using simulation alone.

MCDV’s clock domain analysis tools provides both structural and functional checks, combined with a friendly, easy to use graphical interface to debug issues.

Some key features of MCDV include:

• No testbench required; only required input is the source code
• Identifies master, gated and derived clocks
• Finds clock domain crossings, and recognizes multiple types of synchronizers and user-defined synchronization modules
• Simple and powerful configuration file helps eliminate false errors due to static signals
• Designer’s graphical interface makes it easy to find the source of synchronization problems

Structural and Functional Clock Domain Verification

It is important to check for both structural and functional clock domain synchronization issues. Structural clock domain verification analyzes design connectivity to find problems such as:

• Insufficient synchronization
• Combinational logic driving synchronizers
• Multi-domain combinational logic
• Incorrectly synchronized control and reset signals
• Multibit signals crossing domains through flop-based synchronizers
• Reconvergence of synchronized signals

Graphical Debugging

MCDV is integrated with Designer for efficient debugging of synchronization issues. Textual output is insufficient when debuggin synchronization issues. Often synchronization errors are reported several layers of logic after the real source of the problem. For example, a synchronizer connected to the wrong clock will be reported at the location where the incorrectly synchronized signal is used in another domain.
Designer allows engineers to quickly find the source of clock domain problems using debugging features such as domain colorization and driver/receiver tracing.

• Signals color-coded in source code and schematics to indicate the clock domain
• Clock analysis window link errors to source code; one click shows code causing the problem
• Automatically generated  schematics show cones of logic for clock domain issues such as insufficient synchronization or reconvergent synchronized signals
• Textual report of spreadsheet export available for reading by script or regression analysis or for engineers that prefer text files

MCDV clock domain verification provides a complete solution to quickly and easily find structural and functional clock domain bugs typically missed with simulation methods.