The Design Automation Conference (DAC) is recognized as the
premier event for the design of electronic circuits and systems, and for
electronic design automation (EDA) and silicon solutions. A diverse worldwide
community representing more than 1,000 organizations attends each year,
represented by system designers and architects, logic and circuit designers,
validation engineers, CAD managers, senior managers and executives to
researchers and academicians from leading universities.
This year DAC was held at Moscone Center in San Francisco
from June 4-7. Attendance was up by 16% compared to last year. Exhibit Only
passes were up by 39%. This shows increased interest in EDA tools with users
looking for new tools to solve their design and verification challenges.
This was the best DAC ever for Axiom. We got over 100
visitors with most of them spending significant time in our booth talking to us
and watching the DesignerUVM demo. Over 30% of the visitors asked for a follow up
meeting after DAC, which is unprecedented for any tradeshow.
the show, renowned EDA analyst Gary Smith had predicted that “Debugging” is the
most interesting technology at this year’s DAC; and indeed he was right!
especially UVM debugging was the buzz at DAC, with many papers and tutorials
covering the topic. Many attendees
admitted that debugging UVM models was a big challenge. Axiom’s
recently announced DesignerUVM drew large audience with extremely positive
feedback. The response was overwhelming.
Some of the comments we got were:
“I just presented a paper at the show ranting about the lack
of UVM debug. You guys must have been listening. You guys are so far ahead that
even if you just focus on other things, you will still be ahead of everyone
"I do training in UVM and all my customers are
struggling to understand UVM. I am going to use your product in my
training" – Common theme from all the UVM trainers we talked to at the
"Please set this up for me and I will start developing
my new bench with this"
"When can I get this? The port schematic itself can
save me so much time"
“There is nothing like this out there" – from a
Our newly announced WUL licensing model, allowing users to
have unlimited simulation licenses at a fixed price, also got wide acclaim.
Many visitors agreed that this is what the industry needs.
If you are not already using DesignerUVM to help you
accelerate developing your SystemVerilog/UVM testbenches, contact us. We will
be happy to set you up with a free evaluation licenses so you can experience
the power of DesignerUVM.