Compiled TestBench (CTB)

MPSim has built-in support for advanced testbench features provided by SystemVerilog and the OpenVera™ Hardware Verification language including:

• Classes
• Inheritance and Virtualization
• Interfaces, clocking and virtual ports
• Built-in structures like Arrays, Associative arrays, lists and queues
• Constrained randomization
• Communication structures like Mailboxes, semaphores etc.

The constrained random solver engines are based on formal technology and are guaranteed to find solutions when they exist. By utilizing a compiled constraint solution approach, the MPSim constraint solver can produce results significantly faster than other tools.

Advantages of MPSim’s CTB include:

• Powerful functional coverage analysis
• Support for SystemVerilog and OpenVera™
• Common integrated debugging environment