"Partnering with SysChip's highly committed and experienced team has been very beneficial for NVIDIA as they helped us to tape-out complex Southbridge chip by roping in the RTL freeze schedule by two weeks, enabling us to showcase this product in major events. SysChip owned complete verification activity. The chip booted flawlessly within ten minutes of arrival into our labs. This has saved time and money for NVIDIA. We are extremely happy with their attitude, dedication to NVIDIA's success and timely execution."
Sridhar Manthani
Senior Director
NVIDIA Graphics

"AXIOM has taken a leadership role in the functional verification space by taking advantage of multi-CPU hardware to significantly improve simulation performance. MPSim provides a quantum gain in overall verification productivity necessary to overcome challenges faced by IC design teams working on complex SoC’s."
Atiq Raza
Chairman and Chief Executive Officer
RMI

"The powerful analysis capabilities of @Designer will allow our engineers to more rapidly debug their simulation results."
Chan Lee
Vice President of VLSI Engineering
Ambarella

"The powerful simulation oriented debugging GUI and analysis features of @Designer have allowed our team to find more bugs earlier in RTL development."
Scott Sellers
CTO/VP of Hardware Engineering
Azul Systems

"We are now using MPSim as the default production simulator and have successfully taped out a 40M gate design using this product. MPSim’s integrated OpenVera™, testbench, SystemVerilog assertion and robust debugging capabilities have provided us with an immediate improvement in verification productivity.”
Rajat Roy
VP Product Development and GM of Access and Processor Solutions
RMI

"By utilizing the technical innovations from @HDL, encompassing assertion development, formal model checking , simulation debug and excellent performance, Renesas will see a significant improvement in turn-around-time for our functional verification process."
Yoshio Okamura
Exec. Mngr., Design Technology Div., LSI Product Unit
Renesas

"We are developing high performance communication devices for networking markets, with complex logic interacting across multiple clock domains. Verifier is able to automatically identify functional errors in which logic crossing between domains might not be appropriately synchronized. Using this product has saved us potential design re-spins on several projects."
Andrew Peebles
Director of Engineering
Cortina Systems