News ! Patents Filed for Five Key Algorithms Used in DesignerUVM !
DesignerUVM: The most advanced UVM and RTL Debug and Visualization Environment
Productivity is defined as the amount of time spent in detecting, isolating and fixing design errors and getting a handle on the functional coverage achieved.
Advanced UVM Debug
- UVM Scope and Hierarchy browsing
- UVM Port Connectivity Schematic
- Context Debug
- Virtual Interface connectivity
- Auto transaction waveform
- Config/Resource databases Visualization and write Tracking
- Objections Tracking
- Watch Windows for dynamic objects
- Source annotation
- Advanced Value Change Breakpoints
- Deep UVM Object Data View
UVM Scope and Hierarchy Browser
UVM Port connectivity Schematic
Most Advanced RTL Debug
In order to quickly detect and isolate design errors, a comprehensive state-of-the-art graphical debugger is required. And for maximum efficiency and throughput, it is essential that the debugger be tightly integrated with the simulator in a single kernel environment. MPSim’s Designer is the most advanced graphical debugging environment in a single kernel architecture. Combined with the multi-CPU architecture, Designer offers 2-3X waveform dumping performance. The unified debugger enables simultaneous visualization and debugging of design, testbench, assertions and coverage analysis in a single high performance environment.
Designer’s key features include:
- Tightly integrated with the simulation engine in a single kernel for maximum performance and throughput
- Mixed signal support
- Active driver/receiver tracing from source or waveform
- Execution Tracing - Identifying the lines of RTL code being evaluated at specific time points
- Memory Content Tracing - Viewing the contents of memory as it changes during simulation
- Source code and memory breakpoints – Viewing in post-processing mode
- Automatic dumping of testbench variables and objects
- Support for high level constructs (Mailboxes, Regions, Smart Queues, inheritance etc.
- Concurrent threads display
- Constraint debugging
- Transaction based debugging
- Identifies and analyzes interaction between design, assertions, testbench and coverage
Comprehensive Debugging Environment
- Schematic and block diagram views showing logic values for easy visualization in isolating errors
- Clock domain crossings visualization and debugging
- Seamless and consistent visualization and debugging for RTL, gates, testbenches, assertions, and coverage
- Incremental cone viewing
- Incremental pipeline viewing
- Intelligent X-Tracing mode expands through active logic to find sources of unknown values
- User-defined radices and expressions
- Signal grouping
- DRC, Coverage, Expression Coverage and Clock Domain View
Unique SVA Debug Engine
Designer offers industry’s only SVA Debug engine that allows the user to change assertions and get immediate feedback without re-running simulation. This on-the-fly SVA modification capability enables quick what-if analysis to explore new assertions quickly and efficiently and optimize the tests for highest coverage.
Mixed Signal Support
Designer supports visualization and debugging of mixed analog/digital simulation. Both analog and digital waveforms can be viewed in the same widow for quick debugging and isolating the source of the problem.
Designer has built-in high level constructs for fast and efficient debugging and visualization of testbenches. Debugging of testbenches proceeds concurrently with the design in the same environment. This enables direct correlation between the design and testbenches. Powerful built-in features include support for Mailboxes, Regions, Smart Queues, inheritance, etc.
Low Power Analysis
Designer also facilitates visualization and debugging for low power design. These capabilities include the ability to graphically track the complete power network, visualize the state of all the power switches, as well as the power on/off status of every block in the design through both the source as well as schematic at any point in simulation.
Some key features for low power analysis include:
- Trace complete power network and switches
- Visualize power switch state
- Visualize the state of powered off blocks throughout simulation
- Annotate powered off signals